طراحی و ارزیابی یک واحد چندمنظوره جدید برای سیستم اعداد مانده‌ای پنج‌پیمانه‌ای Class-F با اشتراک‌گذاری منابع سخت‌افزاری

ﻣﺤﻤﺪﺣﺴﯿﻦ   اعظمی راد; اﻣﯿﺮ ﺻﺒﺎغ ﻣﻼحسینی; آزاده   اﻟﺴﺎدات عمرانی زرﻧﺪي; پیمان کشاورزیان

Authors

Mohamad Hosein AzamiRad Department of Computer Engineering, Ke.C., Islamic Azad University, Kerman, Iran Author https://orcid.org/0000-0003-0840-4643
Amir Sabagh Molahoseini Department of Computer Engineering, Ke.C., Islamic Azad University, Kerman, Iran Corresponding author https://orcid.org/0000-0003-3603-9401
Azadeh Alsadat Emrani Zarandi Department of Computer Engineeting. Shahid Bahonar University of Kerman, Kerman Iran Author https://orcid.org/0000-0001-9249-9029
Peyman Keshavarzian Department of Computer Engineering, Ke.C., Islamic Azad University, Kerman, Iran Author https://orcid.org/0000-0001-7383-0169

Keywords:

residue number system, Class, F moduli set, multifunctional unit, hardware resource sharing, reverse conversion, sign detection

Abstract

The residue number system (RNS), by eliminating carry propagation among moduli, enables fast and parallel computation. However, inter-modular operations such as reverse conversion, sign detection, number comparison, and scaling can become major bottlenecks in RNS-based architectures. In this study, a novel multifunctional unit is designed and evaluated for a Class-F five-moduli set with the aim of reducing hardware redundancy and improving the efficiency of inter-modular computations. The employed moduli set is , and the proposed architecture supports modular arithmetic operations, including addition, subtraction, and multiplication, together with reverse conversion, sign detection, signed-number comparison, and scaling within an integrated structure. In the proposed approach, the reverse-conversion core is designed using a staged architecture and the computation of intermediate information, while part of the same hardware resources is reused for sign detection and other inter-modular operations. Furthermore, hardware resource sharing, critical-path reduction, and optimization of the computational structure are employed to control circuit redundancy. The architecture was implemented at the register-transfer level (RTL) and, following functional validation, synthesized using 65-nm CMOS technology and evaluated in terms of area, critical-path delay, and area-delay product (ADP). The results for (n=8), (12), and (26), corresponding to dynamic ranges of approximately 40, 60, and 130 bits, respectively, show that the proposed unit achieves areas of 5,592.9, 9,594.3, and 19,836.9 µm² and critical-path delays of 0.397, 0.439, and 0.526 ns, respectively. The corresponding ADP values are 2,220.3813, 4,211.8977, and 10,434.2094 µm²·ns. The results demonstrate the favorable efficiency of the proposed architecture and the effectiveness of hardware resource sharing in the design of a multifunctional unit for a Class-F five-moduli residue number system.

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